1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a bypass circuit for verifying the characteristics of an internal clock signal.
2. Discussion of the Related Art
Generally, in an input/output (I/O) interface method in which data is transmitted after being synchronized with a clock frequency, for example, when data is transmitted between a semiconductor memory device and a memory controller, it is important to achieve accurate synchronization between a clock signal and the data being transmitted as load on a bus between the semiconductor memory device and the memory controller and the data's transmission frequency increase.
In order to place data at the edge or center of a clock signal, a clock signal having portions allocated for data transmission is reverse compensated for the time taken to load the data on the bus. Accordingly, an internal clock generation circuit, which receives an external clock signal and generates an internal clock signal for each element in the circuit, is used in a semiconductor memory device. An example of a semiconductor memory device using an internal clock signal generation circuit is disclosed in U.S. Pat. No. 6,509,763 entitled, “Semiconductor Device Using Complementary Clock and Signal Input State Detection Circuit Used for the Same”.
FIG. 1 is a block diagram of a semiconductor memory device 10 according to the prior art. Referring to FIG. 1, the semiconductor memory device 10 comprises a clock input buffer 11, an internal clock generation circuit 12, an internal circuit 13, a data output circuit 14, a data input circuit 18, and a command input circuit 23. The clock input buffer 11 receives and outputs an external clock signal (EXCLK). The internal clock generation circuit 12 receives the external clock signal (EXCLK) output from the clock input buffer 11, and generates a plurality of internal clock signals (ICLOCK, TCLOCK, RCLOCK, CCLOCK). The internal circuit 13 comprises a dynamic random access memory (DRAM) core circuit (not shown) and peripheral circuits (not shown), and receives the internal clocks signal (ICLOCK) output from the internal clock generation circuit 12.
The data output circuit 14 receives output data signals (ODATA_ODD, ODATA_EVEN) output from the internal circuit 13, which become synchronized with the internal clock signal (TCLOCK), and outputs an output data signal (ODATA) to the outside (e.g., an external device) through an I/O pad 21. The data output circuit 14 comprises a first phase splitter 15, a multiplexer (MUX) circuit 16, and a data output buffer 17. The first phase splitter 15 receives the internal clock signal (TCLOCK), and outputs complementary output clock signals (TCLK, TCLKB). The MUX circuit 16, which is synchronized with the complementary output clock signals (TLCK, TCLKB), outputs the output data signals (ODATA_ODD, ODATA_EVEN) alternately. In other words, the MUX circuit 16 generates an output data signal (ODATA) in which the output data signals (ODATA_ODD, ODATA_EVEN) are alternately arranged. The data output buffer 17 outputs the output data signal (ODATA) to the I/O pad 21.
The data input circuit 18 comprises a second phase splitter 19 and a data input buffer 20. The second phase splitter 19 receives the internal clock signal (RCLOCK) output from the internal clock generation circuit 12, and outputs complementary input clock signals (RCLK, RCLKB). The data input buffer 20 receives the input data signal (IDATA) through the I/O pad 21. The data input buffer 20 synchronizes the received input data signal (IDATA) with the complementary input clock signals (RCLK, RCLKB) and outputs input data signals (IDATA_EVEN, IDATA_ODD) that are transmitted to the internal circuit 13.
The command input circuit 23 comprises a third phase splitter 24 and an input buffer 25. The third phase splitter 24 receives the internal clock signal (CCLOCK) output from the internal clock generation circuit 12 and outputs complementary command clock signals (CCLK, CCLKB). The input buffer 25 receives a command signal (CMD) through an input pad 22 and is synchronized with the complementary command clock signals (CCLK, CCLKB) and outputs the command signal (CMD) to the internal circuit 13. A dummy output buffer 26 has the same or similar capacitance as the input buffer 25, and functions as a dummy circuit.
The data input/output circuits 14 and 18 and the command input circuit 23, which receives a command signal, perform I/O operations that are synchronized with the internal clock signals (TCLOCK, RCLOCK, CCLOCK). In order, however, to accurately synchronize I/O data, the characteristics of the internal clock signals (TCLOCK, RCLOCK, CCLOCK) are verified as changes in the characteristics (e.g., waveforms, jitter components, duties, etc.) of the internal clock signals influence the I/O data. The characteristics, however, of the internal clock signals can not be verified when the semiconductor memory device of FIG. 1 is in a packaged state.
Accordingly, there is need for a method by which the characteristics of the internal clock signals of a semiconductor memory device can be verified when the semiconductor memory device is in a packaged state.